100. Change CAN Bus Clock to PLLAON
Background
Result
root@nvidia-desktop:~# cat /sys/kernel/debug/bpmp/debug/clk/can1/parent
pll_aon
root@nvidia-desktop:~# ip -d -s link show can0
8: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UP mode DEFAULT group default qlen 10
link/can promiscuity 0
can <BERR-REPORTING,FD> state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 0
bitrate 500000 sample-point 0.870
tq 20 prop-seg 43 phase-seg1 43 phase-seg2 13 sjw 1
mttcan: tseg1 2..255 tseg2 0..127 sjw 1..127 brp 1..511 brp-inc 1
dbitrate 2000000 dsample-point 0.720
dtq 20 dprop-seg 8 dphase-seg1 9 dphase-seg2 7 dsjw 1
mttcan: dtseg1 1..31 dtseg2 0..15 dsjw 1..15 dbrp 1..15 dbrp-inc 1
clock 50000000
re-started bus-errors arbit-lost error-warn error-pass bus-off
0 0 0 0 0 0 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535
RX: bytes packets errors dropped overrun mcast
0 0 0 0 0 0
TX: bytes packets errors dropped carrier collsns
0 0 0 0 0 0
Process
Updating BPMPFW DTB (JAX32)
Updating BPMPFW DTB (JAX64)
Updating Kernel DTB
Last updated